Seminar on VERILOG System

Date : 30 Jan 2019 | Category : Event

The Department of Electronics & Communication Engineering, RIET, Jaipur organized a Seminar on “VERILOG SYSTEM” on 29, Jan 2019. The speaker of this event was Mr. Ankur Saxena, Assistant Professor, ECE. It was attended by all the students and faculties of ECE Department. The session was started at 10:30 am till 12:30 pm at Admin Seminar Hall.

He briefed about Verilog, which is a hardware description language describing a digital system like a network switch or a microprocessor or a memory to model any system before fabrication. Verilog supports a design at many levels of abstraction. The major three are Behavioral level, Register-transfer level, Gate level. He also discussed about the latest advancements and future directions in the area of VLSI design. The students learned design Flow in VLSI and How to model any circuit in HDL.